1. Field of the Invention
The present invention generally relates to divide-by-N circuits for dividing the frequency of a master clock signal in order to obtain a clock signal having a different frequency from that of the master clock signal (also known as frequency dividers). The present invention more particularly relates to a frequency dividing circuit that divides the frequency of a master clock signal by a non-integer.
2. Background Art
Divide-by-N counters (or circuits) are well-known circuits that are used to divide the frequency of a clock signal (e.g., a system clock) by a specific number of counts. That is, for N clock pulses input into the circuit, only one output pulse is generated.
These frequency dividers are used for many different applications. In particular, frequency dividers are used to reduce the overall number of oscillators required on a given semiconductor chip, thereby making available additional room on the chip to place as much other circuitry as possible. Often, a single oscillator circuit is provided that generates a master clock signal. One or more frequency dividers are then used to generate clock signals having different frequencies. Typically, one or more divide-by-2 circuits are used to divide the master oscillator clock frequency by a factor of 2, 4, 8, etc.
It would be desirable to provide a frequency divider that can divide a master clock signal by a non-integer factor. In addition, it would be desirable to have such a frequency divider that can be used for very high speed applications (e.g. >1 Ghz), and that provides a clock signal having very low jitter.